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* MIC841N MACROMODEL
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* Revision 1, 5/2011
* Model platform : PSpice Version 10.0.0
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*
* This Macromodel is a behavioral model that models
* the functionality, output driver output voltage 
* versus current and operating conditions bounds. 
*
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* MODEL LIMITATIONS:
* 
* 1. Propagation Delay (tD) is not modeled. 
* 2. Input Leakage Current (IVIN) is not modeled.
* 3. Input Supply (IDD) is not modeled.
* 4. Model does not consider temperature effects or manufacturing variability. 
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*
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******* BEGIN MIC841N MODEL ***********
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.SUBCKT 841N_core GND OUT VDD VHTH VLTH 
V_V2         $N_0001 0 5
R_R5         $N_0003 $N_0002  1k  
C_C2         0 $N_0002  1p  
V_V1         $N_0004 0 1.24
C_C8         0 VLTH  1p  
C_C7         0 VHTH  1p  
R_R9         0 $N_0005  10MEG  
R_R8         OUT $N_0006  0.1  
C_C9         OUT $N_0006  1p  
C_C6         $N_0007 OUT  1p  
.IC         V($N_0008 )=5
.IC         V($N_0009 )=0
S_SWin         VDD $N_0006 $N_0010 0 SMOD
X_inv1          GND $N_0011 $N_0001 $N_0009 inv_buff
S_SW1         OUT $N_0007 $N_0011 0 SMOD
X_HS5          $N_0007 GND VDD volt_ctrl_res_noutput
X_HS1          $N_0002 $N_0004 $N_0008 $N_0009 comparator
X_HS2          $N_0003 $N_0008 $N_0009 VHTH VLTH MUX_2to1
X_HS3          $N_0010 $N_0005 VDD Disable_block
.ENDS    841N_core

.SUBCKT inv_buff GND INV VCC VIN 
C_C12         GND INV  1p  
S_SW11         $N_0001 GND VIN 0 SMOD
R_Rpu         $N_0001 VCC  1k  
R_Rpu3         INV $N_0001  1k  
C_C17         GND $N_0001  1p  
.ENDS    inv_buff

.SUBCKT volt_ctrl_res_noutput a b VIN 
R_R9         0 HS4_HS5_CTRL  10G  
G_G3         a b VALUE { v(a,b)/v(HS4_HS5_CTRL) }
R_R7         b a  10G  
E_E4         HS4_HS5_CTRL 0 TABLE { V(VIN, 0) } 
+ ( (1.5,37.6) (2.0,20.97) (3.0,12.78) (4.0,9.88) (5.0,8.55) (5.5,8.1) )
.ENDS    volt_ctrl_res_noutput

.SUBCKT comparator In Ref Reset ResetB 
V_V1         $N_0001 0 5V
R_R9         $N_0002 HS4_HS1_nandout4  1k  
R_R10         $N_0003 HS4_HS1_nandout42  1k  
C_C4         0 HS4_HS1_nandout42  1p  
X_inv6          0 Reset $N_0005 $N_0004 inv_buff
.IC         V($N_0004 )=0
X_inv4          0 $N_0006 $N_0005 HS4_HS1_nandout12 inv_buff
X_inv7          0 ResetB $N_0005 Reset inv_buff
E_ABM25         HS4_HS1_nandout12 0 VALUE { if(V(HS4_HS1_nandout42) > 2 &
+  V(HS4_HS1_nandout1) > 2 , 0, 5)    }
X_inv5          0 $N_0004 $N_0005 HS4_HS1_nandout12 inv_buff
E_ABM24         $N_0003 0 VALUE { if(V(HS4_HS1_nandout12) > 2 &
+  V(HS4_HS1_nandout22) > 2 , 0, 5)    }
V_V5         $N_0005 0 5V
E_ABM22         $N_0002 0 VALUE { if(V(HS4_HS1_nandout1) > 2 &
+  V(HS4_HS1_nandout2) > 2 , 0, 5)    }
C_C3         0 HS4_HS1_nandout4  1p  
X_inv1          0 HS4_HS1_nandout3 $N_0001 $N_0007 inv_buff
E_E1         $N_0007 0 TABLE { V(In, Ref) } 
+ ( (0,0) (0.001,5) )
X_inv2          0 $N_0008 $N_0001 HS4_HS1_nandout1 inv_buff
E_ABM23         HS4_HS1_nandout1 0 VALUE { if(V(HS4_HS1_nandout3) > 2 &
+  V(HS4_HS1_nandout4) > 2 , 0, 5)    }
X_HS10          $N_0008 HS4_HS1_nandout2 delay_element_2u
X_HS13          $N_0006 HS4_HS1_nandout22 delay_element_2u_2
.ENDS    comparator

.SUBCKT MUX_2to1 Out Reset ResetB Vhi Vlo 
S_SW2         Out Vhi Reset 0 SMOD
S_SW1         Out Vlo ResetB 0 SMOD
.ENDS    MUX_2to1

.SUBCKT Disable_block OUT OUTBAR VIN 
V_V29         $N_0001 0 5
V_V30         $N_0002 0 1.49
X_nor3          0 $N_0004 $N_0003 OUTBAR OUT $N_0001 or_nor
C_C15         0 $N_0003  1p  
C_C16         0 $N_0004  1p  
E_E9         $N_0003 0 TABLE { V($N_0005, $N_0006) } 
+ ( (0,0) (0.01,5) )
E_E8         $N_0004 0 TABLE { V($N_0002, $N_0005) } 
+ ( (0,0) (0.01,5) )
E_E12         $N_0005 0 VIN 0 1 
V_V31         $N_0006 0 5.52
.ENDS    Disable_block

.SUBCKT delay_element_2u DelayIn DelayOut 
V_V40         $N_0001 0 1
E_E10         $N_0002 0 TABLE { V($N_0003, $N_0001) } 
+ ( (0,0) (0.001,5) )
R_R40         $N_0002 DelayOut  1k  
V_V43         $N_0004 0 2.5
D_D2         $N_0003 $N_0004 DN 1
C_C20         0 DelayOut  1p  
S_SW6         $N_0003 0 $N_0005 0 SMOD
V_V38         $N_0006 0 5
X_inv3          0 $N_0008 $N_0006 $N_0007 inv_buff
G_G5         0 $N_0003 $N_0008 0 1
R_R39         DelayIn $N_0009  1k  
X_inv2          0 $N_0007 $N_0006 $N_0009 inv_buff
C_C22         0 $N_0009  1p  
X_inv1          0 $N_0005 $N_0006 $N_0009 inv_buff
.PARAM         td_2u=2u 
C_C19         0 $N_0003  {5*td_2u}  
.ENDS    delay_element_2u

.SUBCKT delay_element_2u_2 DelayIn DelayOut 
V_V40         $N_0001 0 1
E_E10         $N_0002 0 TABLE { V($N_0003, $N_0001) } 
+ ( (0,0) (0.001,5) )
R_R40         $N_0002 DelayOut  1k  
V_V43         $N_0004 0 2.5
D_D2         $N_0003 $N_0004 DN 1
C_C20         0 DelayOut  1p  
S_SW6         $N_0003 0 $N_0005 0 SMOD
V_V38         $N_0006 0 5
X_inv3          0 $N_0008 $N_0006 $N_0007 inv_buff
G_G5         0 $N_0003 $N_0008 0 1
R_R39         DelayIn $N_0009  1k  
X_inv2          0 $N_0007 $N_0006 $N_0009 inv_buff
C_C22         0 $N_0009  1p  
X_inv1          0 $N_0005 $N_0006 $N_0009 inv_buff
.PARAM         td_2u_2=2u 
C_C19         0 $N_0003  {5*td_2u_2}  
.ENDS    delay_element_2u_2

.SUBCKT or_nor GND IN1 IN2 NOR OR VCC 
R_Rpu         NOR VCC  1k  
R_Rpu2         OR VCC  1k  
S_SWb         NOR GND IN1 0 SMOD
S_SWa         NOR GND IN2 0 SMOD
S_SWin         OR GND NOR 0 SMOD
C_C12         GND NOR  1p  
C_C14         GND OR  1p  
.ENDS    or_nor


*** Switch models ***
.MODEL SMOD VSWITCH ROFF=1G RON=0.001 VOFF=0.4V VON=0.7V
.MODEL SMODN VSWITCH ROFF=1G RON=8.4 VOFF=0.4V VON=0.7V
.MODEL SMODP VSWITCH ROFF=1G RON=31.5 VOFF=0.4V VON=0.7V
.model dn  D(IS=1E-15)

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******* END MIC841N MODEL ***********
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