Foundry






Micrel Fab Division Process Capabilities







Micrel Semiconductor Wafer Fab Division process capabilities. Micrel continually reviews and updates its process and production capabilities as part of our commitment to keep pace with the leading edge of the semiconductor industry. For information on the Company’s most current processes and capabilities, contact your local Micrel sales representative.

MEMS Processes
  MEMS-only or CMOS+MEMS integrated processing
  Inkjet; inertial, pressure, Hall, optical and infrared sensors; microphones, resonators
  Electrostatic actuators, capacitive and piezoresistor sensors
  0.5μ stepper lithography with front-to-back side alignment
  Stitching capability for large die
  SOI (Silicon on Insulator)
  Thick epi-silicon
  Doped/undoped polysilicon
  Thermal, LPCVD and PECVD oxide
  LPCVD and PECVD (low stress) nitride
  State-of-the-art DRIE etch on SPTS Pegasus
  KOH etch
  CMOS-compatible metals; thin and thick metal dry etch
  Coming soon: XeF2, anhydrous HF release

CMOS Processes
  Numerous digital and analog Si-gate technologies, from 0.35μ/3.3V to 16μ/45V
  Stitching capability for large die
  Anisotropically-etched contacts, down to 0.4μ
  Anisotropically-etched poly, pitch down to 0.9μ (.45μ/.45μ)
  Dry-etched metal, pitch down to 1.2μ
  CMOS metal gate technology, down to 5μ/12V
  Double- or triple-poly technology
  Nitride-on-oxide poly-to-poly capacitors
  LDD/NLDD processes for higher voltages
  DDD processes for higher voltages
  1μ, 2μ, 3μ and 5μ extended-drain for higher voltage
  Buried- and surface-channel CCD
  Single- and double-poly EEPROM technology
  Gate oxides, down to 70A
  Military–style nitride-on–oxide metal gate technology
  Rad–tolerant CMOS Si-gate technologies
  Transient-upset protected CMOS (neutron-irradiation)
  N on N+ CMOS for latch-up protection
  P on P+ CMOS for latch-up reduction
  Retrograde P-well and N-well for latch-up reduction
  Optical sensors with nitride-type anti-reflective coating
  Extended-drain CMOS for high voltage (160V)
  Dielectric isolation capability/experience
  Buried-contact for buried-poly-via capability
  CMOS-type bipolar technology and buried Zeners
  Plasma nitride passivation
  Ink-jet CMOS process technology
  15Ω to 1MΩ/sq poly resistors (stabilized)
  Low-noise processes
  Low-leakage processes
  Contrast-enhanced-material lithography
  Zener-trim cells
  Zener-trim

BiCMOS Processes
  Metal-gate CMOS with power NPNs and PNPs
  Option to add metal-gate LDMOS with no additional masks
  In P-well, Si-gate, or metal-gate CMOS technologies, a highperformance vertical PNP (separate collector) may be added with one additional
N-base mask and is supported by predefined macros.
  In P-well, Si-gate CMOS technology, a lateral NPN with good Beta and separate collector may be used and is supported by predefined macros.
  BiCMOS options are available which are fully-isolated (such as bipolar); just N-EPI on N+ starting material, or "No EPI"

Bipolar Processes
  Bipolar processes from 5μ epi/15V to 10μ epi/170V
  Schottky diodes available with AlSiCu or TiSi2/TiN
  Resistor heater module
  Optical sensors with nitride-type anti-reflective coating
  Dielectric isolation capability/experience
  Plasma-nitride passivation
  Poly-interconnect, resistor or fi eld-plate option
  Washed-emitter technology
  Poly-emitter technology
  Characterized up/down isolation technology
  Complementary bipolar
  5μ thick metal dry-etch capability
  Low-noise processes
  Low-leakage processes
  Zener-trim cells
  Implanted buried layer

DMOS Processes
  Discrete devices up to 2GHz and up to 300 Watts
  Dual-well metal-gate DMOS/CMOS technology to 80V
  D.I. version of DMOS/CMOS
  Lateral (Si-gate or metal-gate) or vertical DMOS

Micrel Si-Gate Bipolar/CMOS/DMOS (BCD)
  DMOS/HVPCH and bipolar transistors: 50V, 100V or 200V
  High-voltage CMOS: 45V
  6V, 7V, 8V Zeners/buried Zeners
  Pre-tested analog/digital macros
  5VIN to 200VOUT translators
  H-bridge capability (all-VDMOS)
  Double-poly high-voltage nitride-on oxide capacitor technology
  Depletion devices
  High-voltage resistors: 100V/200V
  High-efficiency voltage tripler
  Stabilized bandgap references
  Over-temperature/over-voltage capability
  Sense-FET capability (on-chip)
  Latch-up-proof process
  LDMOS and VDMOS on same wafer
  High-voltage (100V/200V) gate VDMOS option
  Option for no-body-effect on VDMOS or HPCH