| The SY69753L is a complete Clock Recovery and Data Retiming integrated circuit for OC-3/STS-3 applications at 155Mbps NRZ. The device is ideally suited for SONET/SDH/ATM applications and other high-speed data transmission systems.
Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate source as reference.
The SY69753L also includes a link fault detection circuit. |
- Industrial temperature range (–40°C to +85°C)
- 3.3V power supply
- SONET/SDH/ATM compatible
- Clock and data recovery for 155Mbps NRZ data stream
- Two on-chip PLLs: one for clock generation and another for clock recovery
- Selectable reference frequencies
- Differential PECL high-speed serial I/O
- Line receiver input: no external buffering needed
- Link Fault indication
- 100K ECL compatible I/O
- Complies with Bellcore, ITU/CCITT and ANSI specifications for OC-3 applications
- Available in 32-pin EPAD-TQFP
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